1. Field of the Invention
The present invention relates to a semiconductor device and its design method, and specifically to an interconnection layout capable of preventing circuit malfunctions caused by noise generated by, for example supply voltage fluctuation (power supply noise), and cross talk noise in semiconductor integrated circuits.
2. Prior Art
Noise caused by supply voltage fluctuation (hereinafter, referred to as “power supply noise”) and cross talk noise in integrated circuits have been increasingly so significant as to be non-negligible as a degradation factor of a signal waveform with the progress of high-performance and high-density for LSI products in recent years. The main factor thereof may include such a reason that a signal level and a supply voltage must be reduced according to a MOS scaling rule while there can not be avoided an increase in noise generation in attempting to make CMOS circuits higher in speed. The increase in noise and the reduction in supply voltage make an SN ratio in a high-speed CMOS significantly degrade as far as the circuit is designed by means of employing the conventional technology and circuit design.
Herein, referring to a drawing shown in FIG. 12, description will be made of a conventional semiconductor device. FIG. 12 is a block diagram of the conventional semiconductor device, reference numeral 1 represents a plane virtually showing a (N−1)-th interconnection layer (N is an integer equal to two or more); reference numeral 2, a first signal line comprising a data latch function (latch circuit) formed with the (N−1)-th interconnection layer; and reference numeral 3, a second signal line formed with an N-th interconnection layer.
Hereinafter, referring to the semiconductor device configured as above, description will proceed to that operation. It is assumed at first that data at an L (low) level is retained on the first signal line 2 comprising the latch circuit. In the meanwhile, when a signal at an H (high) level is supplied to the second signal line 3, anode potential of the latch circuit directly beneath the second signal line 3 will become floating according to a coupling effect, so that data in the latch circuit may be inverted when the node potential exceeds VDD/2 (VDD is a power supply potential) which is a judgment level. A superior quality electric power supply has formerly been obtained only by arranging several decoupling capacitors on a substrate in a CMOS based design. However, ΔI noise (current noise) has been a major problem with making the CMOS higher in speed, and in order to reduce this noise, such measures have been taken in the conventional technology that, for example a space between signal interconnections has been made wider, a shield line has been arranged between these signal interconnections, or while a signal interconnection among internal interconnections has been made into a strip line structure in general, an earth (ground) layer or a power supply layer having wide area in so-called plate shaped pattern has been formed via an insulating layer on the upper and lower sides of an interconnection conductor formed as a signal interconnection. There is described a conventional technology in, for example JP-A 11-274424 (the term “JP-A” as used herein means an “unexamined published Japanese patent application”) to prevent an adverse influence caused by the noise due to fluctuation in power supply voltage and the cross talk noise. According to this conventional technology, a ground line with a shield layer is provided on a memory cell, so that the noise generated by the voltage fluctuation on a power supply line is passed through the ground line through the shield layer, and thereby an incorrect inversion of data stored in the memory cell can be prevented.
However, in such an interconnection structure that reduces the noise by making the space between the signal interconnections wider and inserting the shield line or the shield layer between the signal interconnections as described above, an integration degree of the circuit has been inevitably decreased to thereby have a problem in achieving high density interconnection.